The present invention relates to a nonvolatile memory device and a data processing system and, particularly, to a technique effective to be applied to generation of a high voltage in a flash memory, EEPROM (Electrically Erasable Programmable Read Only Memory) and the like.
The inventor herein has examined and found that, for example, a flash memory, EEPROM, or the like is provided with a high-voltage generating circuit for generating an increased high voltage used for writing data.
FIG. 4 shows, as an example, the configuration of a high-voltage generating circuit 40 as a voltage generating unit and its peripheral circuits provided for an EEPROM.
In the peripheral portion of the high-voltage generating circuit 40, a write clock generating circuit 41, a timing control circuit 42, a boost control signal generating circuit 43, a voltage clamping circuit 44, and a memory control circuit 45 are provided.
The write clock generating circuit 41 receives a write command output from a CPU or the like, generates a write clock signal, and outputs the write clock signal to the timing control circuit 42. The timing control circuit 42 controls timings of clock signals and outputs the clock signals to the boost control signal generating circuit 43, memory control circuit 45, and a memory mat 46.
The boost control signal generating circuit 43 generates a control signal for boost from the clock signal output from the write clock generating circuit 41 and outputs it to the high-voltage generating circuit 40. The high-voltage generating circuit 40 increases a power supply voltage, thereby generating an increased power supply voltage. The voltage clamping circuit 44 clamps the increased power supply voltage generated by the high-voltage generating circuit 40 to a certain level and outputs the resultant voltage to the memory mat 46 via the memory control circuit 45.
The high-voltage generating circuit 40 takes the form of, for example as shown in FIG. 5, a charge pump circuit in which a plurality (for example, 24) of depletion-type MOS (Metal Oxide Semiconductor) transistors are connected in series.
In the high-voltage generating circuit 40 taking the form of a charge pump circuit, a capacitance connected to the gate of a transistor is similarly constructed by a depletion-type MOS transistor.
By using the control signal generated by the boost control signal generating circuit 43, the high-voltage generating circuit 40 generates an increased power supply voltage by a charge pumping operation.
A technique of generating an increased power supply voltage in an EEPROM or the like is described by, for example, Masui, Sawada, and Sugawara in literature xe2x80x9cAn On-Chip High-Voltage Generator Circuit for EEPROMs with a Power Supply Voltage below 2Vxe2x80x9d, 1995 Symposium on VLSI Circuit Digest of Technical Papers, 1995. The literature describes a high-voltage generator circuit for efficiently generating an increased power supply voltage by providing a bootstrap circuit for amplifying the amplitude of a clock signal.
The inventor herein has, however, found that the technique of generating an increased power supply voltage by the high-voltage generator circuit as described above has the following problem.
Specifically, to assure charge transfer capability, a number of dedicated depletion MOS transistors having a low threshold voltage are necessary. Consequently, problems arise such that the layout area of a semiconductor chip becomes large and the manufacturing efficiency of a semiconductor integrated circuit device deteriorates.
An object of the invention is to provide a nonvolatile memory device and a data processing system capable of efficiently generating a high voltage, with a reduced layout area of a semiconductor chip without deteriorating the charge transfer efficiency due to dependency on backward bias when a high voltage is generated.
The above and other objects and novel features of the invention will become apparent from the description of the specification and the attached drawings.
Representative aspects of the invention disclosed in the application will be briefly described as follows.
The present invention provides a technique of generating a high voltage in, for example, a semiconductor processing device in which a nonvolatile semiconductor memory as shown in FIG. 2 is mounted. The nonvolatile memory device includes a nonvolatile memory 12 having nonvolatile memory cells, a central processing unit (hereinbelow, CPU) 9, and a high-voltage generating circuit 15 for supplying a predetermined voltage to be supplied to the nonvolatile memory cells. The high-voltage generating circuit generates a predetermined voltage to be applied to a memory cell in each of the operations in accordance with a control from the CPU, and has a control signal generating circuit and a plurality of charge pump unit circuits. The control signal generating circuit generates a control signal to be supplied to the plurality of charge pump unit circuits. The charge pump unit circuit has, for example in FIG. 6, an input terminal 101, an output terminal 105, first, second, and third signal input terminals 102, 103, and 104 for receiving first, second, and third signals, respectively, each signal having an amplitude of a power supply voltage, a power supply terminal 107, and a bias terminal 106 for a well of a predetermined MOS transistor. The second and third signals are signals changing synchronously with the first signal as shown in FIGS. 7 and 8 and changing in predetermined time in a cycle of the first signal. The voltage generating unit is a circuit in which the plurality of the charge pump unit circuits 2001, 2002, 2003, and 2004 are cascaded as shown in FIG. 9, for generating a predetermined voltage. The first signals supplied to an odd-numbered stage and an even-numbered stage of the plurality of cascaded unit circuits have opposite phases as shown in FIG. 10 and each of the second and third signals is generated from the first signal. The charge pump unit circuit has: a function of transmitting a signal to an input terminal 101 via a first capacitor 121 in accordance with a change in the first signal having a change in the amplitude of the power supply voltage supplied; a first MOS transistor 131 for charge transfer whose drain is connected to the input terminal 101 and whose source is connected to an output terminal 105; a circuit 501 for generating and outputting a composite signal of the second and third signals as a fourth signal having a change in voltage between the power supply voltage terminal 107 and the input terminal 101 to a fourth signal output terminal 108; a circuit for transmitting the fourth signal to the gate terminal 109 of the first MOS transistor 131 via a third capacitor 123; a second bias circuit 142 connected between the gate terminal 109 of the first MOS transistor 131 and the input terminal 101; and a fourth MOS transistor 134 whose gate terminal is connected to the output terminal 105. A source electrode and a drain electrode of the fourth MOS transistor 134 are connected to the gate terminal 109 of the first MOS transistor 131 and the input terminal 101, respectively. The fourth signal generating circuit 501 includes a second MOS transistor 132, a third MOS transistor 133, a second capacitor 122, and a first bias circuit 141. The second signal is supplied to the gate terminal 110 of the second MOS transistor 132 via the second capacitor 122, the source and drain of the second MOS transistor 132 are connected to the input terminal 101 and the fourth signal output terminal 108, respectively. The gate of the second MOS transistor 132 is biased to the input terminal 101 by the first bias circuit 141. The gate, source, and drain of the third MOS transistor 133 are connected to the third signal terminal 104, the power supply terminal 107, and the fourth signal output terminal 108, respectively. The well of each of the first and fourth MOS transistors 131 and 134 is connected to the well bias terminal 106, to which a predetermined well bias voltage is supplied.
A concrete circuit of each of the bias circuits 141 and 142 is realized by a resistor shown in FIG. 13, a MOS diode circuit shown in FIG. 14, or a bidirectional MOS diode circuit shown in FIG. 15.
The outline of some additional aspects of the present invention will be briefly described.
1. A Data Processing System
The system includes a nonvolatile memory unit, a volatile memory unit, a central processing unit, and a semiconductor processing device to which an operation instruction signal and an operation voltage are supplied. The nonvolatile memory unit has a plurality of nonvolatile memory cells for storing information and a voltage increasing unit comprised of a plurality of charge pump unit circuits. The voltage increasing unit receives a power supply voltage supplied and generates a first predetermined voltage to be supplied to a nonvolatile memory cell so as to store information to the nonvolatile memory cell. The voltage increasing unit has a control signal generating circuit for generating a clock signal to be supplied to the plurality of charge pump circuits and the plurality of charge pump circuits. The nonvolatile memory unit selects a nonvolatile memory to which desired information is stored, supplies the first predetermined voltage to the selected memory, and stores the desired information to the selected memory.
2. Nonvolatile Memory Device
The nonvolatile memory device has a memory array having a plurality of nonvolatile memory cells, a control unit, and a voltage generating unit for supplying a predetermined voltage to a nonvolatile memory cell. The memory array can store desired information and has a plurality of word lines and a plurality of data lines. The gate electrode of each nonvolatile memory cell is connected to a corresponding word line, and the nonvolatile memory cells are connected to corresponding data lines, thereby forming nonvolatile memory cells in an array. The memory array has one or more groups of nonvolatile memory cells sharing a well region. The control unit controls supply of a voltage generated by the voltage generating unit to a corresponding word line and/or a corresponding well region to erase the information stored in a nonvolatile memory cell. The voltage generating unit has a control signal generating circuit for generating a clock signal to be supplied to the plurality of charge pump unit circuits, and the plurality of charge pump unit circuits.
3. Data Processing System
The system has one or more nonvolatile memory devices and a central processing unit. The nonvolatile memory device has a plurality of nonvolatile memory cells and a voltage generating unit. The nonvolatile memory device instructs the voltage generating unit to generate a predetermined voltage in accordance with an operation instruction from the central processing unit to store, read, or erase information to/from a nonvolatile memory cell. The voltage generating unit has a control signal generating circuit for generating a clock signal to be supplied to the plurality of charge pump unit circuits and the plurality of charge pump circuits. To each of the charge pump unit circuits, a power supply voltage is applied. The charge pump unit circuit at the final stage outputs a predetermined voltage.